Browse Prior Art Database

Data Packer

IP.com Disclosure Number: IPCOM000049540D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 44K

Publishing Venue

IBM

Related People

Dewar, DR: AUTHOR

Abstract

The pack logic circuit eliminates the need to transfer unused data bits to the host computer during a read from a tester's fail buffer by packing only the meaningful data bits, from a tester's fail buffer into X-bit size words prior to transfer to the host computer. This reduces the number of data transfers required between tester and computer during a buffer read. The amount of storage space used by the host is reduced, and a time savings is also realized due to fewer transfers and the fact that the logic can pack the data faster than the computer.

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Data Packer

The pack logic circuit eliminates the need to transfer unused data bits to the host computer during a read from a tester's fail buffer by packing only the meaningful data bits, from a tester's fail buffer into X-bit size words prior to transfer to the host computer. This reduces the number of data transfers required between tester and computer during a buffer read. The amount of storage space used by the host is reduced, and a time savings is also realized due to fewer transfers and the fact that the logic can pack the data faster than the computer.

The packing function is accomplished by loading the fail buffer's data bits into a parallel in, serial out shift register and then shifting only the meaningful bits into a serial in, parallel out shift register. Another word is then requested from the fail buffer and 1 added into the first shift register. The meaningful bits from this word are then shifted into the second shift register. When the second shift register contains the same number of meaningful data bits as the number of bits making up the test system's data bus, a word is ready for transfer to the computer. A more detailed description follows.

Six variables will be used in the detailed description of the logic; they are: m=number of data input lines to the pack logic

n=number of meaningful data bits contained in the fail

buffer on a per address basis

w=number of bits required to express m in binary

x=number of bits making up the test system's data bus

y=number of bits required to express n in binary

z=number of bits required to express x in binary

The logic circuit shown is capable of either passing the input data word from the fail buffer directly to the system data bus or packing n meaningful bits in an m-bit input data word into x-bit size words before placing the data on the system's data bus. This circuit also checks the input word for parity and then assigns bus oriented parity to the word before placing any data on the system data bus.

If a parity error is detected on the input data, the logic is capable of routing this input data and its parity bit to the system data bus.

This word is also assigned bus-oriented parity before being placed on the bus to prevent a bus parity error. The parity checking and generating logic can easily be deleted from the circuit if this feature is not required.

In pack mode, the logic circuit is reset by a 'reset' pulse on reset line 10. The 'pack data' line 11 is held true, and the test system generates a 'load width strobe' on bus 15. This strobe is used to load the 'data width register' 13, and counter 14, with the value of the data present on the system data bus 12. The value of this data is one less than the total number of meaningful bits per address in the fail buffer (n-1). A 'load width strobe' signal on line 15 guarantees that other components in the logic are preconditioned to operate in this pack mode.

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A read pulse on line 16 from the test system (n...