Browse Prior Art Database

Improvement of Hamming Matrix Triple Bit Error Detection Capabilities

IP.com Disclosure Number: IPCOM000049559D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Gerchman, ET: AUTHOR

Abstract

The drawing shows a high-level data flow of the Error Checking and Correction (ECC) function for 8 bytes of data. Within the dashed lines is the additional circuitry necessary to upgrade triple bit error detection to 100 percent.

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Improvement of Hamming Matrix Triple Bit Error Detection Capabilities

The drawing shows a high-level data flow of the Error Checking and Correction (ECC) function for 8 bytes of data. Within the dashed lines is the additional circuitry necessary to upgrade triple bit error detection to 100 percent.

The ECC matrix lies between two 72-bit registers: the memory data register (MDR) 3 and the error correction register (ECR) 5. The 72 bit positions for these registers consist of 64 data bits and 8 parity or check bits (dependent on whether data is being fetched or stored).

The matrix consists of three major functions: (1) the R-bit decoder 7 is a large exclusive OR (EO) function masked over the 64 data bits it receives from the MDR. There are a total of 25 of these R-bits produced (5 per byte), and each one is the EO of some selected bit pattern from the 8 bytes of data. These R- bits, along with the 8 check bits or parity bits (again dependent on fetch or store), are fed into the check bit generator 9.

The check bit generator performs several major functions within the matrix. In the case of a store to memory, it will generate 8 check bits by exclusive ORing certain combinations of the 25 R-bits it receives. These 8 check bits will be stored in memory along with their appropriate byte of data.

In the case of a fetch, this generator will receive the 25

R-bits and try to produce the same 8 check bits it did on the store operation. This time these 8 newly generated check bits are compared with the 8 original check bits coming back from memory. If no errors have occurred, the check bits should match and all syndrome bits will equal 0. If some error occurs, a pattern will develop over the 8 syndrome bits that will aid i...