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Single-Mask Etching Process for Forming a Terminal Via with a Tapered Slope

IP.com Disclosure Number: IPCOM000049563D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Clark, HA: AUTHOR [+4]

Abstract

In this etching process a tapered via profile is obtained with a significant area of nitride exposed for forming an improved bond between the subsequent pad and the device.

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Single-Mask Etching Process for Forming a Terminal Via with a Tapered Slope

In this etching process a tapered via profile is obtained with a significant area of nitride exposed for forming an improved bond between the subsequent pad and the device.

In the fabrication of integrated circuit devices, a surface passivating layer of Si(3) N(4) and an overlying layer of polyimide are deposited over the metallurgy system. It is necessary to form I/O terminals through the composite layer. The vias through the layer should desirably be tapered, and have an area of Si(3) N(4) exposed for improved adherence to terminal pads, i.e., chromium. In addition the polyimide should not be undercut by removal of edge portions of the Si(3) N(4).

In this process the above objectives are achieved. The process consists of depositing, exposing and curing a photoresist layer (not shown) on the surface of the uncured polyimide layer 10 to define desired via openings. The exposed polyimide layer 10 is removed by subtractive etching with a suitable etch, for example, tetramethyl ammonium hydroxide (TMAH). The underlying Si(3) N(4) layer 12 is etched in a CF(4) plasma using the original mask and the uncured polyimide layer 10 to define the area to be etched. Subsequently, the device is exposed to an asher step using O(2) at a power of 475 watts for a period of 15 minutes. This removes any polyimide overhang and provddes a via profile of the type illustrated in the figure. The polyimide is cure...