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Planarized Polysilicon Transistor Structure

IP.com Disclosure Number: IPCOM000049566D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR

Abstract

This is a proposal for achieving improved planarization of transistor structures which comprise polysilicon formations. When polysilicon is used in bipolar technology for the contacts to monocrystalline NPN bases or (lateral) PNP emitters/collectors or for a polysilicon resistor, an additional nonplanarity is created by this polysilicon. This article describes a process which, except for unavoidable nonplanarity of emitter and SBD contacts, results in a highly planarized integrated structure of the above type.

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Planarized Polysilicon Transistor Structure

This is a proposal for achieving improved planarization of transistor structures which comprise polysilicon formations. When polysilicon is used in bipolar technology for the contacts to monocrystalline NPN bases or (lateral) PNP emitters/collectors or for a polysilicon resistor, an additional nonplanarity is created by this polysilicon. This article describes a process which, except for unavoidable nonplanarity of emitter and SBD contacts, results in a highly planarized integrated structure of the above type.

To obtain the structure shown in Fig. 1, initially conventional process steps are performed. N+ subcollector 1 is diffused into a P-substrate, and this is followed by a subisolation diffusion 2.

Then N-epitaxial layer 3 is deposited, oxidized to form oxide 4, a conventional recessed oxide isolation 5 is defined. P-type resistors (not shown) can now be ion implanted or diffused. In a following step oxide 4 is etched to open regions defining collsctor contact 6, PNP transistor 7 and P resistor contacts (not shown). A layer of undoped polysilicon (Poly Si) 8 is deposited and optionally oxidized.

This is followed by chemical vapor deposition (CVD) of Si(3) N(4) 9 and SiO(2) 10. Layers 10 and 9 are then etched in regions outside NPN base 11, collector contact 6, PNP emitter 13 and collector 14, and also outside of P-type resistor contacts and polysilicon resistors. The exposed polysilicon 8 is then partially reactively ion etched (RIE) and oxidized to completion, thus forming oxide regions 15 (between devices) and 16 (in base area of late...