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N-Way and Circuit and Multiplex Circuit for Transistor Logic Family

IP.com Disclosure Number: IPCOM000049577D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Beranger, H: AUTHOR

Abstract

The circuit shown in Fig. 1A is a four-way AND circuit with good noise immunity, which can advantageously be used in a multiplex circuit, as shown in Fig. 1B. The T(2) L compatible noise immunity is given by a reference voltage source which is connected to the transistor emitter of the AND circuit. Input signals are applied to high barrier Schottky diodes.

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N-Way and Circuit and Multiplex Circuit for Transistor Logic Family

The circuit shown in Fig. 1A is a four-way AND circuit with good noise immunity, which can advantageously be used in a multiplex circuit, as shown in Fig. 1B. The T(2) L compatible noise immunity is given by a reference voltage source which is connected to the transistor emitter of the AND circuit. Input signals are applied to high barrier Schottky diodes.

Input signals INl to IN4 are applied to the cathodes of Schottky barrier diodes S1 to S4, respectively, the anodes of which are connected in common to the base of transistor T1 and to the voltage supply VP through resistor R1. The emitter of transistor T1 is connected to reference source 1.

When the inputs are at an UP level, the diodes are OFF and transistor T1 is ON. Output transistor T2 is OFF, and voltage on output OUT is at an UP level.

Up to a 64-way AND gate may be built by dotting the outputs of 16 AND gates as shown in Fig. 1A.

The multiplex circuit shown in Fig. 1B comprises two-way AND gates of Fig. 1A with a common reference source 1.

In each AND gate one input receives a data D, to be multiplexed on output OUT, and a control pulse CTL. Only one control pulse CTL1, CTL2 or CTL3 is up at a time. The output of the multiplex circuit is in phase with the input.

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