Browse Prior Art Database

Power True-Complement Generator

IP.com Disclosure Number: IPCOM000049580D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Grandguillot, M: AUTHOR [+2]

Abstract

The circuit shown above is a power true complement generator for providing input signals to a Schottky barrier diode address decoder.

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Power True-Complement Generator

The circuit shown above is a power true complement generator for providing input signals to a Schottky barrier diode address decoder.

It comprises an input driver stage 1 which transmits the input signal IN on node N1 and two push-pull inverter stages 2 and 3. Circuit 2 provides the out of phase complement signal, and circuit 3 provides the in phase true signal.

Circuit 3 is driven through transistor T1 and resistor R1. Transistor T1 provides on its collector a signal level which is inverted with respect to the input signal level.

Circuit 1 comprises transistors T2 and T3. When the input signal on terminal IN is at an up level, transistor T2 is ON and thus transistor T3 is OFF so that node N1 is at an up level. Thus transistor T1 is ON, and the level on node N2 is down.

Inversely, when the input signal is at a down level, transistor T2 is OFF and transistor T3 is ON. Node N1 is at a down level and node N2 is at an up level.

The inverter stages 2 and 3 comprise the same components. The signal on node N1 is applied to the base of transistor T4 and the signal on node N2 is applied to the base of transistor T'4.

When an up level is applied to the base of transistor T4 or T'4, this transistor is ON, T5 or T'5 is OFF, and T6 or T'6 is ON, so that the output on the emitter of T5 or T'5 is at a down level equal to 1.05 V.

Inversely, a down level on the base of transistor T4 or T'4 causes the transistor to be OFF, transistor T5 or T'5 to be...