Browse Prior Art Database

Central Control Unit Instruction Prefetch Mechanism

IP.com Disclosure Number: IPCOM000049581D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Lechaczynski, M: AUTHOR [+4]

Abstract

The central control unit (CCU) instruction prefetch is a hardware mechanism which allows up to four instructions to be loaded into four preoperation (POP) registers from main storage. Two instructions are loaded into two POP registers at the same time via a 4-byte main store interface. This instruction fetch is overlapped with the instruction execution. The prefetched instructions will be valid and executed unless a branch instruction is predetected.

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Central Control Unit Instruction Prefetch Mechanism

The central control unit (CCU) instruction prefetch is a hardware mechanism which allows up to four instructions to be loaded into four preoperation (POP) registers from main storage. Two instructions are loaded into two POP registers at the same time via a 4-byte main store interface. This instruction fetch is overlapped with the instruction execution. The prefetched instructions will be valid and executed unless a branch instruction is predetected.

The function which is performed through this mechanism is to get instructions from main storage, queue them (four instruction queue) and make them available for the instruction decode/execution logic.

When a pair of POP registers (A,B or C,D) become free, for example, registers A and B, both registers are selected for write and an IPF (Instruction Pre Fetch) BID is issued by control. When this IPF BID is selected by the priority mechanism of the machine, POP registers A and B are loaded and POP input gates are then positioned to C and D. An IPF BID will be issued when POP registers C and D are free. A POP register is free from the time its content is gated to the instruction decode logic to the time it is loaded with a new instruction.

The POP registers are gated to the Instruction Decode Logic in sequence: A, B, C, D, A, B,... on a first in, first out basis. The next POP register is gated out when the "POP SHIFT" order is received from the control circuit, indicati...