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Sense System with Paired Selection of Reference Cells for FET Storages

IP.com Disclosure Number: IPCOM000049586D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Arzubi, L: AUTHOR [+2]

Abstract

There are two different reference systems presently used in the design of one-device cell (1 Dcell) sense systems. 1) I/O capacitive coupling, and 2) direct capacitive coupling (DCC).

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Sense System with Paired Selection of Reference Cells for FET Storages

There are two different reference systems presently used in the design of one-device cell (1 Dcell) sense systems. 1) I/O capacitive coupling, and

2) direct capacitive coupling (DCC).

The figure shows a circuit using the DCC approach. The reference level is generated by means of capacitances C1 and C2. Assuming that the voltage on word line WL1 goes up and transfers the data from cell node CN to bit line BL on the left, then reference voltage REFL B is forced to go down, so that the difference C2 - C2(low) is effective for generating the respective reference level.

If a cell on the other side of the sense latch is selected, reference voltage REFL A is forced to go down, and the difference C1 - C1 (low) on the other side generates the reference level.

When comparing the reference scheme proposed herein with the state of the art, the following advantages become apparent. Use of DCC permits a simpler and easier layout of the

reference cells.

Use of a differential reference scheme permits almost ideal

tracking between C and C(low), thus eliminating tracking

noise and improving the signal to noise ratio.

As a reference capacitor activates the various lines on

both sides of the sense latch, both sides are mode coupled,

thus reducing the noise still further.

The aforementioned approach leads to an easier implementation (layout) of the reference scheme as well as to a substantial improvement of the si...