Browse Prior Art Database

Two-Phase Clocked Latch

IP.com Disclosure Number: IPCOM000049588D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

One of the most commonly used clocking systems has two latches, a master latch (MASTER LT) and a slave latch (SLAVE LT) for one unit of storage (Fig. 1). For the shift function, the latches are separately driven by shift clock A and shift clock B, whereas for normal operation, they are driven by clocks A and B. All clocks are non overlapping pulse trains, as shown in Fig. 2. Such a design is generally free from hazards.

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Two-Phase Clocked Latch

One of the most commonly used clocking systems has two latches, a master latch (MASTER LT) and a slave latch (SLAVE LT) for one unit of storage (Fig. 1). For the shift function, the latches are separately driven by shift clock A and shift clock B, whereas for normal operation, they are driven by clocks A and B. All clocks are non overlapping pulse trains, as shown in Fig. 2. Such a design is generally free from hazards.

For saving components, for example, for denser on chip structures, the latch back function of the master latches can be eliminated, as shown in Fig. 3. For a non-hazardous operation, shift clock A pulses must be longer than shift clock B pulses and be non-overlapping (Fig. 4).

However, the master multiplexer, the input stage of the eliminated master latch, must ensure a minimum propagation delay or a sufficiently high electromagnetic inertia. In bipolar technology, this can be achieved, for example, by high resistance transistor, capacitive or inductive loads. The necessary skew between clocks A and B can be adjusted automatically by known circuitry according to the delay tolerances of the LSI or VLSI manufacturing process.

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