Browse Prior Art Database

Process for FET with Short Channel Defined by Shallow Extensions of Drain and Source Diffusions

IP.com Disclosure Number: IPCOM000049594D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Tsang, YL: AUTHOR

Abstract

An FET (field-effect transistor) has relatively deep N/+/ diffusions where the metal contacts for the drain and source terminals are located, and it has thin extensions of these diffusions up to the edges of the channel. The thin diffusion and a sealed gate structure permit the edge of the channel to be formed more accurately and reliably.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

Process for FET with Short Channel Defined by Shallow Extensions of Drain and Source Diffusions

An FET (field-effect transistor) has relatively deep N/+/ diffusions where the metal contacts for the drain and source terminals are located, and it has thin extensions of these diffusions up to the edges of the channel. The thin diffusion and a sealed gate structure permit the edge of the channel to be formed more accurately and reliably.

In Fig. 1, an oxide layer is formed on a silicon wafer 2 and is etched to form posts 3. The posts are used as a mask in several later steps. A nitride etch step opens an area in the oxide between the posts where the gate of an FET is to be formed and areas outside the posts where the metal contacts for the drain and source are to be formed.

A much thinner oxide layer 4, 4' is formed over these openings.

In the opening for the gate, this oxide forms the gate insulation. This oxide layer will later be removed in the area 4' where the metal contacts for the drain and source terminals will be formed.

A thick layer of polysilicon is formed over the thick oxide 3 and the thin oxide 4 of the gate insulation. In the area of the gate, the polysilicon will form the gate electrode 5 and it will be removed from the other areas. This polysilicon layer is etched by an isotropic process that substantially levels off the top surface of the polysilicon with the top of the oxide mask, as shown in Fig. 1.

Then an isotropic oxide etch removes the thin o...