Browse Prior Art Database

Se1f-Aligned GaAs MESFET Process

IP.com Disclosure Number: IPCOM000049605D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Andrade, TL: AUTHOR

Abstract

A self aligned gallium arsenide metal Schottky gate FET (MESFET) device and process is disclosed which avoids the need for a refractory gate metal structure, which will withstand the heating cycle necessary to activate the source/drain implant.

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Se1f-Aligned GaAs MESFET Process

A self aligned gallium arsenide metal Schottky gate FET (MESFET) device and process is disclosed which avoids the need for a refractory gate metal structure, which will withstand the heating cycle necessary to activate the source/drain implant.

Fig. 1 illustrates the beginning of the process where a semilayer of approximately 1000 angstroms in thickness of an N-type gallium arsenide 2. On top of the layer 2 is applied a thick photoresist 3. The layer 3 is followed by a 3000 angstroms thick layer of aluminum or other metal 4. The layer 4 is then followed by a thin photoresist layer 5 having a thickness of approximately 5000 angstroms.

A pattern is defined in the top resist layer 5 followed by the etching of the aluminum layer 4. The bottom resist layer 3 is then blanket exposed and developed, leaving the relatively tall structure which is shown in Fig. 2.

Next, an ion implantation of silicon ions 6 or other donor ions for gallium arsenide, is made using the photoresist layer 3, the aluminum layer 4 and the photoresist layer 5 as an ion implantation mask.

On top of the structure shown in Fig. 2, there is layer deposited a two component material, such as a 1 Mum silicon monoxide layer 7 and a 1000 angstroms chromium layer 8, as shown in Fig. 3.

Next, the resist layer 3 is dissolved and lifted off, and the entire structure is capless annealed. The structure is heated to approximately 800-850 degrees C for several minutes with an arsen...