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Condition Code Register

IP.com Disclosure Number: IPCOM000049621D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Lemaire, CA: AUTHOR [+2]

Abstract

In the IBM System/38 (see Processing Unit Theory Maintenance Manual SY3l-0524), the IMPI (Internal Microprogram Instruction) condition code was stored in a reserved local storage register (LSR). The IMPI condition code required a series of horizontal microcode (HMC) control words to set and test it in the reserved LSR. By providing a separate condition code register, a significant performance improvement is achieved. The condition code register is a two-bit register which can be accessed and modified by the microcode in a manner similar to other hardware registers. Additional function has been added to the end operation (EO) control word to set the condition code and to the instruction fetch (11) control word to test the condition code.

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Condition Code Register

In the IBM System/38 (see Processing Unit Theory Maintenance Manual SY3l-0524), the IMPI (Internal Microprogram Instruction) condition code was stored in a reserved local storage register (LSR). The IMPI condition code required a series of horizontal microcode (HMC) control words to set and test it in the reserved LSR. By providing a separate condition code register, a significant performance improvement is achieved. The condition code register is a two-bit register which can be accessed and modified by the microcode in a manner similar to other hardware registers. Additional function has been added to the end operation (EO) control word to set the condition code and to the instruction fetch (11) control word to test the condition code.

The condition code register clocks, the condition code register and the encoding logic for setting the condition code register either as an arithmetic and logic unit (ALU) destination or as specified by the EO condition code control field sre shown in Figs. 1, 2 and 3. The EO control word has been modified to include the condition code control field. Bits 18-20 inclusive of the EO control word specify the condition code control field. The format of the new EO control word is shown in Fig. 4.

The logic for generating the LACC (L-Register ANDed with CC-Register Decode) branch condition for the I1 control word is shown in Fig. 5. The logic for decoding the CC register into 4 bits to be used as data input into the ALU is shown in Fig. 6. The ALU input bits 0-3 are not shown because they are always zero when the condition code register is used as a source.

Instructions setting the condition code can load the condition code register by any of the three following methods: 1. Use the condition code register as a destination in a

control word. In this instance the condition code register

is loaded with the encode of the 0 bus bits 12-15,

as shown in Fig. 7.

2. In an EO control word. the condition control register

is conditionally set based upon the state of bits

in the S-register (not shown) and on the encode method

specified...