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Dynamic Non-Volatile and Electrically Erasable Read Only Memories

IP.com Disclosure Number: IPCOM000049679D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR [+2]

Abstract

A dynamic semiconductor memory cell is made non-volatile by utilizing a four-port or terminal floating gate device including a graded band gap or silicon-rich insulator. This non-volatile cell may be modified to provide an independent electrically erasable read-only memory. Graded band gap or silicon-rich insulators are described in U.S. Patents 3,972,059 and 4,104,675.

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Dynamic Non-Volatile and Electrically Erasable Read Only Memories

A dynamic semiconductor memory cell is made non-volatile by utilizing a four-port or terminal floating gate device including a graded band gap or silicon- rich insulator. This non-volatile cell may be modified to provide an independent electrically erasable read-only memory. Graded band gap or silicon-rich insulators are described in U.S. Patents 3,972,059 and 4,104,675.

In normal operation of the cell illustrated in Fig. 1, voltages of appropriate magnitude are applied to first and second control gates Ve and Vw of a four-port non-volatile device 10 and to electrode Vp to form a storage node 11 between first and second N+ diffusion regions 12 and 14 formed in silicon substrate 16. A line R connected to third N+ diffusion region 18 is used to transfer volatile data to a nonvolatile mode. Normally the four-port non-volatile device 10 is in "on" condition to permit charge flow to and from N+ diffusion region 12, which acts as the bit line, when a word pulse is applied to the word line WL as in a conventional one-device cell. Third diffusion 18 is capacitively coupled to storage node 11 by means of variable capacitor 19 having a thin layer of silicon dioxide 20 disposed between the surface of substrate 16 and a conductive layer 22, preferably made of doped polysilicon, connected to second N+ diffusion region 14 which is connected to the storage node 11.

To transfer data from the storage node 11 to the floating gate FG of the four- port non-volatile device 10, first control gate Ve and line R are pulsed to a higher voltage. If the voltage at storage node 11 is at a high value, e.g., +5 volts, representing a 1 binary digit, the voltage on storage node 11 is also driven to a higher potential by line R, producing an insufficient voltage differential across graded band gap or silicon-rich insulator 24 to cause electrons to flow from floating gate FG to first control gate Ve. Thus, there is no change in the characteristic of the non-volatile device 10. If, however, the voltage at storage node 11 is at a low value, e.g., zero volts, representing a 0 binary digit, the high voltage applied to line R has no significant effect on storage node 11 and, therefore, the voltage differential across graded band gap insulator 24 is relatively large, producing electron flow from floating gate FG to first control gate Ve causing floating gate FG to become positively charged. This positive charge on floating gate FG transforms non-volatile device 10 from an enhancement device to a depletion device.

It should be noted that the transformation from enhancement to depletion still allows normal dynamic operation of the cell without affecting the data in the non- v...