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Plated Through Hole Fault Simulation Test Board

IP.com Disclosure Number: IPCOM000049685D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Summa, WJ: AUTHOR [+2]

Abstract

The wall to wall spacings between adjacent holes formed in the dielectric layer of a printed circuit test board are varied in a controlled manner to provide the board with different insulation resistances between different pairs of adjacent holes.

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Plated Through Hole Fault Simulation Test Board

The wall to wall spacings between adjacent holes formed in the dielectric layer of a printed circuit test board are varied in a controlled manner to provide the board with different insulation resistances between different pairs of adjacent holes.

To evaluate the effects of material and/or process changes associated with the manufacture of the prototype, in one known system a printed circuit board (PCB), incorporating the material and/or process changes and having multiple holes in the pattern corresponding to the standard drilled plated through hole (PTH) pattern of the prototype, is used as a test board. The PTH to PTH insulation resistance between the test board's adjacent holes or predetermined pairs of adjacent holes is tested for short-circuit faults due to insulation resistance failure of the board dielectric between adjacent holes as a result of the afore mentioned changes. However, the standard hole diameter of the standard drilled hole pattern and the standard pattern itself produced so few insulation failures that it was difficult to provide meaningful evaluations. In the known system, to provide more simulated failures, it was necessary to change the standard drilled PTH pattern. However, the resulting deviation from the standard pattern was a typical and once the evaluation data could not be readily correlated with the reference data obtained from a reference prototype with which it is compared.

The pre...