Browse Prior Art Database

Bipolar Transistor Process

IP.com Disclosure Number: IPCOM000049702D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A process is described for fabricating compact, high-performance NPN bipolar transistors in integrated circuit form.

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Bipolar Transistor Process

A process is described for fabricating compact, high-performance NPN bipolar transistors in integrated circuit form.

The initial steps of fabrication are similar to those of conventional arrangements where the process commences with a P-type wafer 2, as shown in Fig. 1. Then, there is successively formed N+ subcollector region 4, P+ subisolation region 6, N- epitaxial layer 8, SiO(2) layer 10, recessed oxide isolation (ROI) region 12, N+ reach-through region 14 and P base region 16. The transistor structure at this stage of processing is shown in Fig. 1.

The processing then proceeds with deposition of a layer 18 of about 1,600 Angstroms of Si(3)N(4) and a layer 20 of 2-3 KA of pyrolytic SiO(2). Using photolithography, windows are opened in the composite of SiO(2) layer 20 and Si(3)N(4) layer 18. Layers of approximately 1.0 um of polysilicon 22, 500 angstroms of Si(3)N(4) 24 and 500-800 angstroms 2, of pyrolytic SiO(2) 26 are then successively deposited. Polysilicon layer 22 may preferably be doped N+ in situ for the purpose of facilitating its etching in later processing.

Using photolithography and CF(4) reactive ion etching (RIE), windows are etched in the composite of SiO(2) layer 26 and Si(3)N(4) layer 24. Then, using argon/chlorine RIE, exposed polysilicon layer 22 is etched so as to obtain practically vertical sidewalls to the etched polysilicon patterns.

A layer 28 approximately 0.8-1 um thick of pyrolytic SiO(2) is then deposited. Exploiting vertically directional RIE, SiO(2) layer 28 is thereafter etched away, leaving practically unaltered those portions flanking the sidewalls of polysilicon patterns 22. The resulting transistor structure is shown in Fig. 2. The RIE process is continued to etch away SiO(2) layer 26 and exposed SiO(2) layer 10. As shown in Fig. 3, a layer 30 about 250 Angstroms tick of ther,a; SiO(2) is optionally grown at the stage stage over exposed silicon to serve as a screen oxide, if required, during subsequent ion implantation.

A blockout photoresist mask is formed and used to etch away selected portions of SiO(2) 28, as desired. The next process step involves implantation of an approximate 6 X 10/15//cm/2/ dose of arsenic ions into the silicon just beneath SiO...