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Process for Forming Multiple Conductive Surface Polysilicon Electrode Isolation

IP.com Disclosure Number: IPCOM000049704D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Barile, CA: AUTHOR [+4]

Abstract

In this improved process, flaws in the insulating sidewall oxide between two polysilicon layers are minimized or eliminated through the use of directional plasma etching.

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Process for Forming Multiple Conductive Surface Polysilicon Electrode Isolation

In this improved process, flaws in the insulating sidewall oxide between two polysilicon layers are minimized or eliminated through the use of directional plasma etching.

In double polysilicon structures, the first or lower doped polysilicon layer 12 is deposited and subsequently covered with an oxide layer 14. Before depositing the second overlying polysilicon layer, the underlying layer 12 must be subtractively etched to form the desired pattern. When oxide layer 10 is removed by wet etching techniques, oxide layer 10 as well as the overlying oxide layer 14 are etched horizontally, resulting in overhanging portions of layer 12, as indicated in Figure 2B. When the surface of the substrate is reoxidized, as in forming the gate oxide 16, a wedge oxide 18 is formed, as shown in Figure 3. The extent to which wedge oxide 18 is formed is dependent on the undercut, and the oxidation and doping conditions. When the second polysilicon layer is deposited over the surface shown in Figure 3, flaws or cracks, which develop or exist at the wedge oxide location, will form shorts between the second polysilicon (not shown) and the polysilicon layer 12.

In this process, photoresist layer 20 is deposited over layer 14, as indicated in Figure 1, and the areas exposed through opening 22 of layer 20 are removed by directional plasma etching, resulting in a vertical wall through layers 14, 12 and 10, as in...