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Process for Forming a Contact Hole Stud

IP.com Disclosure Number: IPCOM000049708D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Lange, RC: AUTHOR [+4]

Abstract

In this process a stud or plug is formed in an oxide layer overlying a semiconductor device. The stud preserves the planar surface of the oxide layer, thus permitting a more uniform metallurgy system.

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Process for Forming a Contact Hole Stud

In this process a stud or plug is formed in an oxide layer overlying a semiconductor device. The stud preserves the planar surface of the oxide layer, thus permitting a more uniform metallurgy system.

In forming the metallurgy on an integrated circuit semiconductor device, the use of lift-off techniques with contact openings with steep sidewalls, formed with reactive ion etching (RIE) techniques, can result in severe topography over contact openings through the oxide layer.

In this process, the device consists of a monocrystalline silicon substrate 10, fashioned with various devices (not shown), with an overlying layer 12 of SiO(2) or other passivating material. In forming the contact stud, a lift-off layer 14, typically of polysulfone material, is deposited as a blanket layer over layer 12, and a layer 16 of aluminum deposited on its surface. A resist layer 18 is deposited on layer 16, exposed and developed to form an opening 20 over the location of the desired contact opening. As shown in Fig. 1, an opening is formed in layer 16 using RIE techniques with a plasma formed of CCl(4).

As shown in Fig. 2, opening 22 is formed in layer 14 using RIE techniques with a plasma which includes O(2). As indicated in Fig. 3, the opening 22 is extended through layer 12 using RIE techniques with a plasma formed of CF(4). Subsequently. the metallurgy layers desired in opening 22 are deposited on the surface of the device. For example, a l...