Browse Prior Art Database

Very Dense One Device FET Memory Cell

IP.com Disclosure Number: IPCOM000049709D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A processing method is described which leads to very dense one-device FET memory cells having the following main features: Polysilicon-gate FET with conventional micron/submicron deep source diffusion on one side of the gate and several microns deep drain diffusion on the other side of the gate. Source and drain are self-aligned with respect to the gate, the deep drain having alignment-independent dimensions at the same time.

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Very Dense One Device FET Memory Cell

A processing method is described which leads to very dense one-device FET memory cells having the following main features: Polysilicon-gate FET with conventional micron/submicron deep source diffusion on one side of the gate and several microns deep drain diffusion on the other side of the gate.

Source and drain are self-aligned with respect to the gate, the deep drain having alignment-independent dimensions at the same time.

To the extent that further conventional polysilicon-gate FETs with both source and drain of micron/submicron depth are required on typical memory chips for inclusion in peripheral circuitry, the proposed processing method facilitates the same.

A preferable processing method is the following:
1. Start with P- type substrate 2. In a conventional way, form thick field SiO regions 6, preferably of the "recessed" type, with "channel-stopping" P regions 4 beneath them.
2. Form thin gate oxide 8 and, as a preferred option, selectively etch portions of it.
3. Deposit a typical, submicron thick layer of polysilicon (POLY) 10; using photoresist mask 12, form patterns in the polysilicon 10, preferably using reactive ion etching (RIE). Fig. 1 essentially illustrates the resulting cross-section of the one-device FET cell at this stage. Then, preferably by RIE, etch exposed portions of thin SiO(2) 8.
4. Retaining photoresist 12, form patterned photoresist 14 through conventional photoresist coating, masked exposure and photoresist development.
5. With photoresist 12, 14 as mask, etch several microns deep "wells" 16 in silicon, as shown in Fig. 2. As an option, the thick SiO 6 may also serve as a partial mask during well etching. Etching these wells is typically done by RIE in a reactor using CCl(2), HCl and nitrogen. 6. Remove photoresist, and diffuse an N dopant in the exposed silicon and polysilicon, forming doping regions 18 as show...