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Browse Prior Art Database

Planar Self Aligned Metal/ Sidewall and Polysilicon Resistor Process

IP.com Disclosure Number: IPCOM000049714D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Goth, GR: AUTHOR [+3]

Abstract

Self-aligned metal (SAM) processes, such as that described in the IBM Technical Disclosure Bulletin 23, 4928-4929 (April 1981) typically provide metal to metal separation of approximately 0.8 (mu) m. Consequently, lift-off processes are normally employed for global wiring. Described here is a method and structure to be used with the SAM process such that narrow and wide metal line separations are obtained simultaneously. Contrary to the lift-off process, the entire wafer has planar first metal structure.

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Planar Self Aligned Metal/ Sidewall and Polysilicon Resistor Process

Self-aligned metal (SAM) processes, such as that described in the IBM Technical Disclosure Bulletin 23, 4928-4929 (April 1981) typically provide metal to metal separation of approximately 0.8 (mu) m. Consequently, lift-off processes are normally employed for global wiring. Described here is a method and structure to be used with the SAM process such that narrow and wide metal line separations are obtained simultaneously. Contrary to the lift-off process, the entire wafer has planar first metal structure.

The process begins with screen oxidation 17 of the substrate in conventional manner, followed by a first polysilicon layer deposition approximately 1 (mu) thick. Fig. 1 shows the first polysilicon layer 1 on silicon substrate 3. Silicon nitride layer 5 is then deposited by CVD (chemical vapor deposition) to a thickness of approximately 160 nm. Conventional photoresist is then employed to form openings in the silicon nitride layer which define the metal to metal spacer definition. Reactive ion etching is subsequently employed to etch through the polysilicon located at the silicon nitride openings.

The arrangement is then thermally oxidized to approximately 800 angstroms, as shown at 7 in Fig. 2. A layer of silicon nitride 9 is subsequently deposited to approximately 500 angstroms by chemical vapor deposition. This is followed by a deposition of a second polysilicon layer approximately 7000 angstroms thick, a portion of which is shown at 11 in Fig. 2. The second layer of polysilicon is then etched by reactive ion etching with a substantial portion of the polysilicon sidewalls, as shown at 11, remaining. This etching step is followed by thermal oxidation of the second polysilicon layer, resulting in oxide layer 13 being formed, as shown in Fig. 2. The oxidation step is, in turn, followed by another rea...