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Superior Performance NPN Transistors and Polysilicon Resistors

IP.com Disclosure Number: IPCOM000049716D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A process is described for simultaneously realizing polysilicon rs resistors and NPN transistors having improved performance characteristics.

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Superior Performance NPN Transistors and Polysilicon Resistors

A process is described for simultaneously realizing polysilicon rs resistors and NPN transistors having improved performance characteristics.

Starting with P/-/ type substrate 2, the structure shown in Fig. 1 is first fabricated through well-known techniques. In this regard, N/+/ region 4 and P/+/ region 6 are the subcollector and isolation regions, respectively. Likewise, N/-/ region 8 is the epitaxial region. A deep dielectric isolation, which is typically filled with SiO(2), as shown at 12, has a shallow P region 10 beneath it. Fig. 1 also sFows SiO(2) (14)/Si(3)N(4) (16) composite islands which have, as one of their purposes, the function of defining two of the four sides of the emitter and intrinsic base regions.

Preferably through chemical vapor deposition (CAVD), an approximately 1 (mu) m thick SiO(2) layer 18 is formed and, by using photolithography, patterns are formed in the SiO(2) layer approximately at the center of the transistor structure. After forming a photoresist mask 19, the exposed silicon is etched to a suitable depth, as shown in Fig. 2. Thereafter, an approximately 400 angstroms thick layer 20 of SiO(2) d is formed over the over the exposed silicon, and an approximately 500 angstroms thick er Si(3)N(4) layer 22 is deposited. In this regard, the thickness of the thick SiO(2) regions 18 and 12 remain practically the same during the growth of the 400 angstroms thin SiO(2) layer 20.

Through photolithography, a photoresist mask is formed at 23. Then using vertically directional reactive ion etching, the exposed Si(3)N(4) layer 22 is etched leaving practically unharmed portions of Si(3)N(4) layer 22 which flank the vertical sidewalls of the cross-section, as shown in Fig. 3. Thereafter, an approximately 1 (mu) m thick layer 24 of thermal SiO(2) is grown over exposed silicon. Portions of silicon (and SiO(2) 18/12) covered by Si(3)N(4) remain unoxidized. In addition, the thickness of the thick SiO(2) layer 12 remains practically unchanged, even in regions not covered by Si(3)N(4).

The exposed portion of Si(3)N(4) layer 22 is then dip-etched away in a controlled manner, leaving relatively thicker Si(3)N(4) layer 16 unaffected. The cross-sectional structure at this stage is illustrated in Fig. 4. Thereafter, through CVD, approximately 1.5 (mu) m thick layer 26 of poly silicon is formed. A layer of photoresist is applied so as to obtain a practically planar top surface. Using reactive ion etching and adjusting the reactive ion etching conditions for practically the same etch rate for the planarizing material and polysilicon 26, the planarizing material and polysilicon are etched until the top surfaces of SiO(2) islands 18 are exposed, as shown in Fig. 5. Thereafter, using a photoresist mask 27, boron (or another P-type dopant) is ion-implanted to form P-type region 28 in the exposed polysilicon, as shown in Fig. 6. Using another photo resist mask 29, an N-t...