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PNP Charge Storage for Reducing the Power Requirements of Decoder Circuits in Semiconductor Storages

IP.com Disclosure Number: IPCOM000049727D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Keinert, J: AUTHOR [+4]

Abstract

For storage chips with bipolar transistor cells, in which the number of bit channels (bits = N) corresponds to a stored word, one bit line pair has to be simultaneously addressed in each of the N channels for reading or writing. Thus, each bit decoder controls N read/write circuits, each being arranged in another channel.

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PNP Charge Storage for Reducing the Power Requirements of Decoder Circuits in Semiconductor Storages

For storage chips with bipolar transistor cells, in which the number of bit channels (bits = N) corresponds to a stored word, one bit line pair has to be simultaneously addressed in each of the N channels for reading or writing. Thus, each bit decoder controls N read/write circuits, each being arranged in another channel.

To reduce the power requirements, the emitter of the switching transistor TS is controlled by an internal clock signal. In the standby state, transistor TS and decoder TD are off, as the emitter of transistor TS and the inputs of decoder TD are charged to the potential VH.

In the illustrated circuit, a capacity in the form of a highly saturated current mirror PNP-A/PNP-B is provided between line BS and the line for supply voltage VH, so that prior to switching on transistor TS by clock line CL, node A of line BS is capacitively coupled to voltage VH. For selecting transistor TS, clock line CL is pulled from an up level (1.4 volts) to a down level (0.1 volt). At the same time, the capacity applied to line BS is discharged by the base-emitter diode of transistor TS and base resistor R2. As the base current when a transistor is switched on has an AC and a DC component (AC component: charging the base-emitter capacity; and DC component: maintaining the collector current according to the (beta) value of the respective transistor), the full AC current can be drawn from this additional capacity on line BS. After charging of the base- emitter capacity (clock line CL at down level), the base current required (DC component) is low, so that a high value can be chosen for resistor R1 and only a very low current is drawn by the no selected N-1 bi...