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Low Power Fast Bootstrap Inverter with Power Switch-off Scheme

IP.com Disclosure Number: IPCOM000049731D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+2]

Abstract

A fast bootstrap inverter with very low power dissipation is proposed, as the gates of the load field-effect transistors (FETs) are discharged for most of the input signal up time.

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Low Power Fast Bootstrap Inverter with Power Switch-off Scheme

A fast bootstrap inverter with very low power dissipation is proposed, as the gates of the load field-effect transistors (FETs) are discharged for most of the input signal up time.

Fig. 1 is a circuit diagram of the proposed inverter, and Fig. 2 is a timing diagram of the voltages at different circuit nodes and the current supplied to load FETs 1 and 5.

The circuit diagram shows a known bootstrap inverter consisting of FET 1, 2, 5 and 6 as well as capacitor C1. The gates of FETs 1 and 5 are connected to each other and to one electrode of capacitor C1. The node D thus formed can be discharged to ground through FETs 8 and 4. By means of a signal supplied from a circuit for enabling the proposed inverter, which is represented as block 9, node D can be precharged through FET 4. In addition. output IE of this circuit is connected to an inverter 10, which is also represented as a block. Output IEI of inverter 10 is connected to gate G4 of FET 4 through FET 11, whose gate is linked with the positive pole VH of the supply voltage source. The gate and source of FET 4 are coupled by a bootstrap capacitor C4. Load capacitance CL is connected to output O of the proposed inverter. Through FET 12, whose gate is linked with the positive pole VH of the Supply voltage source, output O of the proposed inverter is connected to a capacitor C2 arranged parallel to the source/gate path of FET 8.

The operation of the inverter is such that as soon as the voltage rises at output IE of circuit 9 for enabling the inverter, this rise is transferred to node D through FET 4, whose gate G4 was precharg...