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Browse Prior Art Database

Exclusive OR Circuit

IP.com Disclosure Number: IPCOM000049752D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Boyle, DH: AUTHOR [+3]

Abstract

An improved exclusive OR circuit is disclosed, embodied in NMOS FET technology, which provides a cross-coupled exclusive OR topology having an output which drives an FET push-pull output driver circuit.

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Exclusive OR Circuit

An improved exclusive OR circuit is disclosed, embodied in NMOS FET technology, which provides a cross-coupled exclusive OR topology having an output which drives an FET push-pull output driver circuit.

Referring to the figure, when the input A and the input B are both zero or low voltage signals, then device 1 and device 2 are both off and no current passes through node C. Thus node C has a high potential which is converted by the push-pull inverter comprising devices 8, 9, 10 and 11, into a low voltage or binary zero output. If both A and B are binary ones or relatively high input signals, then both transistors 1 and 2 are conductive and current is passed from the load transistor 5 through the transistor 1, providing a low potential, thereby turning transistor 4 off and current passes from the transistor 6 through the transistor 2, providing a low potential on the gate of transistor 3, turning transistor 3 off. This results in no current flowing through the node C. Node C thus has a relatively high potential which is converted by the push-pull inverter to a binary zero or low voltage output. If either the input signal A or the input signal B is a binary one and the other input is a binary zero, then current will flow through the node C, bringing about a binary one or high voltage output.

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