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Substrate Wiring Patterns for Partial Good Integrated Circuit Chips

IP.com Disclosure Number: IPCOM000049783D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Johnson, CL: AUTHOR [+2]

Abstract

Partial-good memory programs are able to utilize chips which are not completely functional. For instance, if 4 good bits per chip were needed, a chip could be designed with 5 bits, allowing 1 bit to be bad. This will greatly improve usable chip yields. However, chip packaging becomes more complicated. In this instance, five different substrate designs would be needed to accommodate the five different combinations of 4 good data bits.

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Substrate Wiring Patterns for Partial Good Integrated Circuit Chips

Partial-good memory programs are able to utilize chips which are not completely functional. For instance, if 4 good bits per chip were needed, a chip could be designed with 5 bits, allowing 1 bit to be bad. This will greatly improve usable chip yields. However, chip packaging becomes more complicated. In this instance, five different substrate designs would be needed to accommodate the five different combinations of 4 good data bits.

A solution to this problem is to design the chip and matching substrate footprint such that several different positions of the chip on the substrate allow good data bits to be routed correctly. Correct positioning here means either rotational or linear movement over the chip site to adjust for a particular bit configuration.

Fig. 1 shows an integrated circuit (IC) chip 10 having rows of solder-ball contacts 11. Fig. 2 shows a substrate wiring pattern 20 with one position of chip 10 in dashed lines. In this position, the actual positions of contacts 11 are shown as black dots. In this position, contact 12 represents a bad bit, and makes no connection. Data bit contacts 13-16 are good bits, and connect to data lines 21- 24. If, instead, contact 13 should be found to be a bad bit, moving chip 10 downward one row will disconnect contact 13, as shown as 13', and will connect contact 12 to data line 21. Moving chip 10 downward from this position will successively disconnec...