Browse Prior Art Database

Tag Handling for Pointers

IP.com Disclosure Number: IPCOM000049789D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Hoffman, RL: AUTHOR [+3]

Abstract

Pointers in a computer system as described in U.S. Patent 4,241,396 are sixteen bytes and are protected by the use of tag bits. Tag bits cannot be accessed at the instruction interface and cannot be set on by the user. Any attempt by the user to modify the contents of a pointer causes the tag bits to be set off by the hardware, making the pointer invalid for addressing purposes. Tag bits pose a problem, however, because they can add to storage size. In U.S. Patent 4,241,396, storage words are 40 bits where one of the bits is a tag bit. The 40-bit and 72-bit storage words are conventional and available. The 40-bit storage word has 32 data bits, 7 ECC (Error Correcting Code) bits and 1 tag bit. The 72 bit storage word has 64 data bits, 8 ECC bits and none available for a tag bit.

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Tag Handling for Pointers

Pointers in a computer system as described in U.S. Patent 4,241,396 are sixteen bytes and are protected by the use of tag bits.

Tag bits cannot be accessed at the instruction interface and cannot be set on by the user. Any attempt by the user to modify the contents of a pointer causes the tag bits to be set off by the hardware, making the pointer invalid for addressing purposes. Tag bits pose a problem, however, because they can add to storage size. In U.S. Patent 4,241,396, storage words are 40 bits where one of the bits is a tag bit. The 40-bit and 72-bit storage words are conventional and available. The 40-bit storage word has 32 data bits, 7 ECC (Error Correcting Code) bits and 1 tag bit. The 72 bit storage word has 64 data bits, 8 ECC bits and none available for a tag bit. Also, tag bits are stored with data on disk storage. The data is stored The data is stored as 8-bit bytes, and this causes incompatibility with the tag bits which must be separated from the data before being stored on disk.

One solution to the tag bit problem is to store the tag bits in a separate storage. This enables the storage word size to be compatible with conventional storage word sizes. This also eliminates the need to separate tags from data before writing the tags on disk. In order to fetch, reset and store a selected tag bit during a main storage cycle, the storage for tag bits must be at least twice as fast as main storage. High speed storage is expensive and because there is one tag bit for each 16 bytes of storage, it would be desirable to keep tag storage as small as possible, even though there are a large number of tag bits to be stored. The solution for minimizing the cost of tag storage is to use main storage for non- active tag bit storage and high performance storage for active tag bit storage.

The page directory 50 (Fig. 1), which is used in connection with the translation of virtual storage addresses, is modified so as to include a 32-bit tag field 51 for each entry in the page directory to provide one tag bit for each sixteen bytes, there being 512 bytes in a page. Additionally resolved address registers (RARs) 100, which hold the translated main storage address (Fig. 2), are Modified to include a tag storage address 101. The RAR 100 functions to save main storage addresses translated from virtual storage addresses to facilitate sequential accesses to data within a page. Thus whenever a main storage address is obtained from a RAR 100, a tag storage array address is also obtained. The virtual address translator 200 (Fig. 2) is shown in block form in Fig. 3 where the main storage address and the tag storage address from translator 200 address main storage 10 and tag storage 20, respectively.

Each entry in tag storage array 20 is 32 bits, one bit for each 16 bytes (pointer) in a 512-byte page. The array 20 contains the same number of entries as there are in lookaside buffer 220 of virtual address translator 200...