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Implementation of Refresh Memory in Microprocessor Controlled Displays

IP.com Disclosure Number: IPCOM000049830D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Canton, DA: AUTHOR

Abstract

In a microprocessor-controlled display, some of the memory is usually used to store the information that is displayed on the screen. This memory has to be accessed by both the microprocessor and by the display refresh logic. The dual use of this memory causes timing and control problems. It means that the memory must have a faster cycle time than required by the microprocessor or refresh logic alone. Also, if the microprocessor and refresh logic are required to run on different cycle times, then conflict of memory access can occur and this can degrade the microprocessor's performance. It is proposed that the common memory should be implemented in separate storage.

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Implementation of Refresh Memory in Microprocessor Controlled Displays

In a microprocessor-controlled display, some of the memory is usually used to store the information that is displayed on the screen. This memory has to be accessed by both the microprocessor and by the display refresh logic. The dual use of this memory causes timing and control problems. It means that the memory must have a faster cycle time than required by the microprocessor or refresh logic alone. Also, if the microprocessor and refresh logic are required to run on different cycle times, then conflict of memory access can occur and this can degrade the microprocessor's performance. It is proposed that the common memory should be implemented in separate storage.

As shown in the drawing, random-access memory (RAM) 1 is used only by the microprocessor. Hence, there is no interference from the refresh logic. RAM 2 is read by the refresh logic and is also written by the micro. Data is written into RAM 2 at the same time as into RAM 1. However, RAM 2 is separated from the micro by a cache buffer. This cache prevents the microprocessor from interfering with the refresh logic during writing. The size of the cache will depend upon the relative timing of the microprocessor and refresh logic cycles. In most displays the cache will only have to hold the address and data for a single write. Note that the cache does not have to handle reads since the microprocessor reads from RAM 1 only.

The advantages o...