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Saturating Video Driver

IP.com Disclosure Number: IPCOM000049832D
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 4 page(s) / 43K

Publishing Venue

IBM

Related People

Ainscow, F: AUTHOR

Abstract

The video driver in a CRT display is required to switch its output voltage between two well-defined levels, about 50 volts apart. A saturating driver has the inherent advantage that its output can be made to switch between levels which are within a fraction of a volt of the supply voltage rails. This leads to minimum dissipation and allows the use of relatively low breakdown voltage transistors. Unfortunately, a saturating driver suffers from the storage delay phenomenon in the on transistors, and this has prevented its use in high performance displays. However, by careful design of the timing and impedance of the base-driver waveforms, a saturating driver can be made, which switches at least as fast as existing non-saturating circuits, while retaining the advantages of saturation.

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Saturating Video Driver

The video driver in a CRT display is required to switch its output voltage between two well-defined levels, about 50 volts apart. A saturating driver has the inherent advantage that its output can be made to switch between levels which are within a fraction of a volt of the supply voltage rails. This leads to minimum dissipation and allows the use of relatively low breakdown voltage transistors. Unfortunately, a saturating driver suffers from the storage delay phenomenon in the on transistors, and this has prevented its use in high performance displays. However, by careful design of the timing and impedance of the base-driver waveforms, a saturating driver can be made, which switches at least as fast as existing non-saturating circuits, while retaining the advantages of saturation.

Fig. 1 shows the essential elements of the circuit. The incoming video signal is fed to two separate timing circuits 1 and 2 which define the base driver waveforms for two output transistors Q1 and Q2. The timing circuits can also be used to accomplish pulse-stretching, if required. Two base-driver circuits 3 and 4 define the voltage and current levels and source impedances at the bases. Fig. 2 shows the required base-drive waveforms.

In the quiescent condition, resistor R holds the output at the high (OFF) level, and Q1 and Q2 are both off. When the input requires the circuit to switch to the 'ON' state, the following sequence of events occurs:
1. Immediately a control signal is sent to the PNP drive circuit

1 to ensure that Q1 base is driven positive,

thus turning Q1 off if it had been on, and holding

it off against the negative impulse coupled

through Q1 collector-base capacitance (COB).
2. After a short delay, t(1), the Q2 base is driven positive,

and a large base current is allowed to flow. This

turns Q2 on very rapidly, and a large collector current

flows, driving the output negative.

The principal limit on the output slew rate is the

current in Q2, collector-base capacitance, COB, which

subtracts from the available base drive current

(see original).
3. After a further period, t(2), which is long enough to allow

the output transistion to be completed, the base

drive current to Q2 is reduced to a level which is

just sufficient to hold Q2 in saturation against the

load current (principally V+/R). This reduces

the dissipation to a minimum, and minimizes the

current-dependent portion of Q2 base emitter

emitter capacitance (CIE).

The circuit remains in this condition indefinitely, until

the input requires it to switch back to the

'OFF' state, whereupon:
4. Immediately, the Q2 base is driven negative. An initial

current flows out of the base as the CIE is

discharged, leaving Q2 turned off. R is chosen

1

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so that the time-constant it forms with the total

capacitance on the output node is long compared to t(3), so

the output voltage remains substantially at

the 'ON' level after Q2 turns off.
5. After a delay, t(3), Q1 ba...