Browse Prior Art Database

Intermediate Status/ Control Feature

IP.com Disclosure Number: IPCOM000049850D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

Currently in the IBM Series/1 processors, the exchange of status or control information without disturbing the original commend is not permissible.

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Intermediate Status/ Control Feature

Currently in the IBM Series/1 processors, the exchange of status or control information without disturbing the original commend is not permissible.

A status/ control feature is described that allows the exchange and that is compatible with current Series/1 programming. In this feature, a common block of main storage is provided where both the processor and the Input/Output device controller may exchange status and responses.

In the drawing, the control word of the Device Control Block has (1) a Device Dependent field set to some unique value to inform the controller that this new function is active. The Device Parameter 4 at (2) must be an address pointing to the Device Immediate Status Block (DISB) at (3).

The length and format of the Device Immediate Status Block is set by the design of each particular controller. Also, by design the controller may read and/or write to the Device Immediate Status Block, as may be required.

To report immediate status, the controller deposits the status information into the Device Immediate Status Block, sets the Update (U) flag on and presents an Attention Interrupt. The processor will respond by examining the status block and resetting the U flag.

To present immediate control information to the controller, the processor loads the information into the Device Immediate Status Block. The Execute (E) flag is set to signal that the new controls are loaded. The controller senses the flag, accepts...