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Device for Generating Addresses, Data, and Control Words for Memory and Logic Testing

IP.com Disclosure Number: IPCOM000049864D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Nelson, JC: AUTHOR [+2]

Abstract

An addressable, programmable unit (APU) of logic is used to generate arithmetically and logically the addressing, data and control required by a product under test end can be used as an address generator, data generator or for sequencing control words for the test of array or logic products.

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Device for Generating Addresses, Data, and Control Words for Memory and Logic Testing

An addressable, programmable unit (APU) of logic is used to generate arithmetically and logically the addressing, data and control required by a product under test end can be used as an address generator, data generator or for sequencing control words for the test of array or logic products.

The unit of logic is software driven and is capable of producing complex data schedules with a minimum of hardware implementation.

Utilization of this device is based on identifying the components of a function that must be done in real time and those that can be performed off line. Tasks which do not require real time interaction are pre-processed, and the resulting data set is loaded in the buffer. The remaining tasks are implemented via micro- code.

The architecture permits compound nesting of test loops in the control word sequencer configuration. Complex mapping techniques are made possible in the address and data generator configurations.

This addressable programmable unit of logic is shown in the figure wherein a control random-access memory (RAM) 10 holds micro-word commands to control the operation of an arithmetic logic circuit 11 and a multiplexer circuit 12 feeding the logic circuit 11.

The control RAM 10 is directed by stored programs on line 13 from a tester (not shown) while the multiplexer 12 is fed from an address bus 14 and bus 15 carrying variable sets.

The logic circuit 11 is provided with a carry-in line 16 and with a feedback loop 17, and feeds a buffer random-access memory 18 coupled between a data- in bus 19 and a data-out bus 20.

A bit schedule is loaded into the buffer 18 through the multiplexer 12 and arithmetic logic circuit 11. The schedule can be either a binary or decimal count by ones or any random arrangement determined by software algorithms.

The arithmetic logic circuit 11 output addressing the buffer 18 is used to select the buffer contents either as the contents were stored or by a count generated by the arithmetic logic. Buffer addresses are generated by summing the A input from the multiplexer 12, the B input from the feedback loop 17, and the carry-in (Cin) signal on line 16 as directed by the control m...