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Versatile Switching Regulator Oscillator

IP.com Disclosure Number: IPCOM000049873D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Carroll, LB: AUTHOR

Abstract

A switching regulator oscillator is provided with free-running and various synchronized modes by various interconnecting circuit configurations to its input and output.

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Versatile Switching Regulator Oscillator

A switching regulator oscillator is provided with free-running and various synchronized modes by various interconnecting circuit configurations to its input and output.

It is often desirable to operate switching regulators in frequency synchronization. This is especially important when the bulk and bias supplies are shared by several regulators and control circuit decoupling is somewhat inadequate. It also helps in power system debug since interaction of several different regulators may appear as a regulator stability problem. Electromagnetic interference (EMI), radio frequency interference (RFI), and conducted power line noise can also be reduced in a power system if all switching regulators are first synchronized and then phase shifted such that each draws current pulses from its bulk and bias supplies at different times. This switching regulator oscillator circuit is capable of free-running or being synchronized with similar oscillator circuits by simply plugging a cable from one switching regulator to another. With the proper choice of a single resistor, i.e., resistor 28 Fig. 1A, the synchronization process can be made slowly, enabling synchronism or de- synchronism while the switching regulators are operating.

Components 20, 21, 22, and 23 (Fig. 1A) form a standard astable oscillator which exhibits a sawtooth waveform 24 at node 2 and a negative going pulse train 25 at node 3. Timer 20 is a typical conventional timer, e.g., National Semiconductor LM555. Components 26 and 27 are unloaded transistor- transistor logic (TTL) non-inverting buffers. Buffer 26 isolates the low impedance up level of timer 20 and drives the external cabling. Buffer 27 noise isolates the sensitive input node 5 to timer 20 and terminates the external cabling. Resistor 29 pulls up input 40, effectively open circuiting node 5 whenever node 40 is not being pulled down or used. Resistor 28 forces a small voltage drop at nodes 5 and 30 whenever node 40 is pulled down.

When the circuit of Fig. 1A is used in a switching regulator as the switching frequency oscillator and no synchronism is required with other switching regulators or pulse sources, input/outputs (I/Os) 40 and 41 are left open (Fig. 2A). When synchronism is required, its input 40 is connected by the external cabling to the desired synchronizing source. The input pulses appear as a pulse train 42 and can vary slightly in frequency. Thus, in the case of Fig. 2B, input 40 of the oscillator (OSC) of the switching regulator (SW REG 1) is connected by external cable to an auxiliary pulse source (AUX PULSE SOURCE). In Fig. 2C, the inputs 40 of the oscillators of switching regulators 2 and 3 (Fig. 2C) are commonly connected to the output 41 of the oscillator of SW REG 1, designated appropriately as the reference or master oscillator of the system, as the other oscillators are tied in sync, i.e., slaved, to it.

Appropriate delay/single-shot circuitry may be provid...