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On-Chip Microcoding of a Microprocessor with only Most Frequently Used Instructions of a Large System

IP.com Disclosure Number: IPCOM000049874D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 31K

Publishing Venue

IBM

Related People

Agnew, PW: AUTHOR [+6]

Abstract

The performance of a processor is strongly influenced by the length of its critical path from the control store, to the data flow, to the conditional next microword address generator, and back to the control store. A microprocessor, which contains the entire critical path within one chip, can have a very short critical path, and hence a short microcycle time, without expending large amounts of power driving control store addresses and microwords across chip pins. However, currently foreseen microprocessors are limited to an on-chip control store size that will contain only about one quarter of the microcode necessary to implement a mainframe architecture.

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On-Chip Microcoding of a Microprocessor with only Most Frequently Used Instructions of a Large System

The performance of a processor is strongly influenced by the length of its critical path from the control store, to the data flow, to the conditional next microword address generator, and back to the control store. A microprocessor, which contains the entire critical path within one chip, can have a very short critical path, and hence a short microcycle time, without expending large amounts of power driving control store addresses and microwords across chip pins. However, currently foreseen microprocessors are limited to an on-chip control store size that will contain only about one quarter of the microcode necessary to implement a mainframe architecture.

The necessary microcode can be partitioned with only the most commonly used microcode, for fixed point and branching instructions, on chip. In a typical instruction mix, these instructions account for 95 percent by frequency of occurrence, and for 60 percent to 75 percent by execution time. Thus, it is very useful to have these instructions implemented by on-chip microcode with a fast cycle time.

However, it is also necessary to provide a data path by which microwords can be brought onto the microprocessor chip, and provide an off-chip control store to the chip to implement instructions and functions whose microcode will not fit on the microprocessor itself.

This could be done in several cycles using the existing address and/or data pins for the microword bits, or it could be done using dedicated pins. The off-chip control store must be wide enough for both the microword bits and microword selection bits that are required by the sequencer. The off-chip microword sequencer must have access to on-chip st...