Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Partitioning Microcode for a Microprocessor Based Mainframe by Placing Least Frequently used Vertical Microwords Off-Chip

IP.com Disclosure Number: IPCOM000049876D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Agnew, PW: AUTHOR [+6]

Abstract

Current microprocessors achieve excellent cost/performance by allowing a single chip to contain both the control store and the data flow that it controls. Their cost/performance is further improved if the control store is wide or "horizontal", rather than narrow or "vertical". A wide control store eliminates most decoding, so it reduces both complexity and propagation delay. However, a wide control store must contain more bits than a narrow one, to implement a given function.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

Partitioning Microcode for a Microprocessor Based Mainframe by Placing Least Frequently used Vertical Microwords Off-Chip

Current microprocessors achieve excellent cost/performance by allowing a single chip to contain both the control store and the data flow that it controls. Their cost/performance is further improved if the control store is wide or "horizontal", rather than narrow or "vertical". A wide control store eliminates most decoding, so it reduces both complexity and propagation delay. However, a wide control store must contain more bits than a narrow one, to implement a given function.

Currently foreseen microprocessors have insufficient on-chip control store to implement all of the microcode that is necessary to implement an architecture as complex as that found in a mainframe. Yet there is a major cost/performance advantage in having all of the horizontal microcode on the same chip as the dataflow (to avoid the many pins or bus cycles required to bring a wide control word onto the chip), and there is a cost/performance advantage in having the most frequently used vertical microwords on the same chip as the data flow (to avoid any off chip bus accesses in most microcycles). This leaves only the infrequently used vertical microwords to be stored off the microprocessor chip, in a microprocessor-based implementation of a large system or mainframe architecture.

Two detailed design problems can be solved as follows. First, branch from on-chip to off-chip vertical microcode by: A) setting a latch attached to a microprocessor output pin;

B) restricting on-chip vertical micro read-only memory (ROM),

for example, to 512 words, and branching to a word

whose address exceeds 511; and

C) branching to the highest valid on-chip vertical microword

address after setting the off-chip vertical microword

branch address onto the data bus.

Second, allow conditional branches to depend on status bits by: A) b...