Browse Prior Art Database

High/ Low Performance TTL Masterslice Logic Cell

IP.com Disclosure Number: IPCOM000049888D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Currie, GA: AUTHOR [+4]

Abstract

The high/low performance option is achieved by tapping the resistors of the TTL logic cell at the personality (contact) level. Therefore, circuit performance is selected via "book metal" only (global wiring is not affected).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

High/ Low Performance TTL Masterslice Logic Cell

The high/low performance option is achieved by tapping the resistors of the TTL logic cell at the personality (contact) level. Therefore, circuit performance is selected via "book metal" only (global wiring is not affected).

Fig. 1 illustrates schematically how cell performance is selected. By selecting the indicated contacts in the book metal shape rule, the desired resistor valves are obtained.

Fig. 2 illustrates the circuit schematic diagram. Note the circuits are identical except for resistor value changes of R2 and R3.

Fig. 3 illustrates the circuit speed power curve. The high and low performance points are indicated.

Fig. 4 illustrates the cell physical layout. Note that contact personalization is made under the first level metal power bus (fixed metal).

Fig. 5 illustrates cell grouping. Note that the cells are mirrored in such a way that resistor contacts remain independent.

The cell size is not altered by this technique. The maximum ratio of high/low performance circuits is a function of package cooling capacity. Wafer substock is not affected, since resistor value is determined by contact personalization.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]