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TTL Cell with Maximum Wirability

IP.com Disclosure Number: IPCOM000049892D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Crispi, FJ: AUTHOR [+5]

Abstract

A high density masterslice requires a higly wirable cell with a preformance range of about 2 ns at 0.3 mw typical. Figs. 1, 2 and 3 present the schematic and layouts of a TTL (transistor-transistor logic) implementation. The resistors are of an implant/diffused combination arranged such that the values could be fine tuned by adjusting the separate components without affecting the overall cell size. This allows the cell to be optimized by the wiring channel pitch, with no excess wasted space.

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TTL Cell with Maximum Wirability

A high density masterslice requires a higly wirable cell with a preformance range of about 2 ns at 0.3 mw typical. Figs. 1, 2 and 3 present the schematic and layouts of a TTL (transistor-transistor logic) implementation. The resistors are of an implant/diffused combination arranged such that the values could be fine tuned by adjusting the separate components without affecting the overall cell size. This allows the cell to be optimized by the wiring channel pitch, with no excess wasted space.

All contact holes are part of the personalization of the cell such that the usable wiring channel count on first level metal can be nine horizontal, if the cell is not used, or five horizontal, if it is. Up to five possible input point positions are available for increased accessibility.

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