Browse Prior Art Database

Vertical JFET Integrated with Self Aligned Bipolar Process

IP.com Disclosure Number: IPCOM000049894D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Gaur, SP: AUTHOR [+3]

Abstract

An N channel JFET (junction field-effect transistor) is described using bipolar technologies. The JFET device has low threshold voltage with tight tolerance. The device may be implemented in enhancement or depletion form by threshold adjustment. The process provides very tight control of the channel length. Also, there is no extra masking or process step, if a Poly resistor or a specific resistivity is required.

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Vertical JFET Integrated with Self Aligned Bipolar Process

An N channel JFET (junction field-effect transistor) is described using bipolar technologies. The JFET device has low threshold voltage with tight tolerance. The device may be implemented in enhancement or depletion form by threshold adjustment. The process provides very tight control of the channel length.

Also, there is no extra masking or process step, if a Poly resistor or a specific resistivity is required.

The bipolar process for fabricating the JFET is as follows: In Fig. 1, conventional bipolar fabrication techniques are employed to implement the N subcollector 2, P+ isolation 4, N epi 6, recessed oxidation 8, N+ reach-through for the collector 10 and oxide 12/nitride 14 passivation of the top surface of the silicon wafer. A window is opened in the nitride to define the active device region. One-micron thick polysilicon 16 is deposited, followed by a layer of nitride 18. Conventional photoresist masking masking steps and reactive ion etching (RIE) are used to open windows 20 for the emitter and collector regions in the polysilicon.

A 0.8-micron thick layer of CVD oxide is deposited and reactive ion etched to form sidewalls of oxide 22 around the vertical edges of the polysilicon, as shown in Fig. 2. A blockout mask and dip etching (or RIE) is used to open the emitter window and implant N+ arsenic for the emitter P+ boron for the JFET channel followed by emitter drive-in. Emitter 24 and P channel 26 (for the JFET) are thus formed. Photoresist or polyimide 28 is spun and etched back by RIE to planarize the wafer surface and expose the nitride layer 18. The nit...