Browse Prior Art Database

JFET Structure

IP.com Disclosure Number: IPCOM000049896D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

An oxide sidewall, reactive ion etching technique is used to fabricate a double-gated junction field-effect transistor (JFET).

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JFET Structure

An oxide sidewall, reactive ion etching technique is used to fabricate a double-gated junction field-effect transistor (JFET).

The structure shown in Fig. 1 is made in a conventional manner and comprises a p substrate 1, deep oxide filled trench 2, N+ subcollector 3, recessed oxide isolation (ROI) 4, N+ collector reach-through 5 and N- epi region
6.

A p-doped polysilicon layer 7 of about 3,000 A is deposited on the structure of Fig. 1 and is covered by chemical vapor deposited (CVD) oxide 8 of about 1,500 A thickness. A block-out mask is placed over the channel region between deep trench 2 and ROI 4, and the poly and oxide layers are etched away to yield the result of Fig. 2.

A Schottky barrier contact area 9 is opened through layers 7 and 8 and CVD oxide 10 of about 3,000-4,000 Angstroms is deposited and is then reactively ion etched away from all horizontal surfaces. Source and drain areas 11 and 12 are formed by drive-in from the p-doped poly. Contacts 13 and 14 are made to the source, and drain regions 16 are added to complete the structure. The Schottky and the subcollector areas are used as the gates of the JFET.

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