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Array Word Redundancy Scheme

IP.com Disclosure Number: IPCOM000049899D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR [+2]

Abstract

In advanced array design, in order to improve system performance, additional system functions often are implemented on chip to perform output data manipulation. A common add-on function for cache application is variable output word length flexibility. With this added logic on chip, the array can be read in word length of 8 bits, 6 bits, 4 bits, and so on. Due to this particular output structure, redundancy design in the usual bit dimension is almost not possible. Word redundancy is considered to be more practical. This article discloses a word redundancy scheme designed to be used on variable organization arrays. An outstanding feature of this scheme is that it has no delay impact on the chip's AC performance. The scheme can also be adapted for any arrays requiring word redundancy.

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Array Word Redundancy Scheme

In advanced array design, in order to improve system performance, additional system functions often are implemented on chip to perform output data manipulation. A common add-on function for cache application is variable output word length flexibility. With this added logic on chip, the array can be read in word length of 8 bits, 6 bits, 4 bits, and so on. Due to this particular output structure, redundancy design in the usual bit dimension is almost not possible. Word redundancy is considered to be more practical. This article discloses a word redundancy scheme designed to be used on variable organization arrays. An outstanding feature of this scheme is that it has no delay impact on the chip's AC performance. The scheme can also be adapted for any arrays requiring word redundancy.

Fig. 1 shows the schematic of this word redundancy scheme as applied to a typical 8K array. This array is assumed to be organized in a 128-word x 64-bit matrix. The basic 128 word lines (W0 to W127) can be thought of as being divided into 8 groups of 16 word lines each. An additional group of 16 word lines (W128 to W143, total 1K bits) is added to the chip for redundancy. During normal array operation, 7 word addresses are needed to decode 1 out of 128 word lines. Addresses A0 to A2 are used to select one of the 8 word groups, then addresses A3 to A6 will further select 1 out of 16 word lines within the selected group.

Four additional inputs (RA0-RA2 and RENB) are also required to control the redundancy operation. Redundancy address RA0 to RA2 are used to specify deselection of any one of the 8 non-redundant word groups, in case of defects. These 3 address lines are input through 3 redundant address receivers, which drive the "1 out of 8 group disable" circuitry to deselect the corresponding defective word group. This particular defective group will then be replaced by the redundant word group (see Fig. 2).

As shown in Fig. 2, selection of the redundant word group is controlled by a comparator circuit. The redundant address RAB-RAZ and the group Address A0-A2 are both input to a 3-bit comparator. When addresses A0 to A2 match with the preset RA0 to RA2, the output of the comparator will be high. The 16-word decoders in the redundant group are therefore enabled. If A0-A2 does not compare with RA0-RA2, the comparator's output will be low...