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Low Voltage Inverter Receiver Circuit

IP.com Disclosure Number: IPCOM000049900D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Mosely, JM: AUTHOR [+2]

Abstract

The circuit shown will receive off-chip signals and provide on-chip low voltage inverter circuit compatible logic signals. The low voltage inverter (LVI) circuit is more fully described in Electronics 4, 412 (February 24, 1981) and in U.S. Patent 4,283,640.

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Low Voltage Inverter Receiver Circuit

The circuit shown will receive off-chip signals and provide on-chip low voltage inverter circuit compatible logic signals. The low voltage inverter (LVI) circuit is more fully described in Electronics 4, 412 (February 24, 1981) and in U.S. Patent 4,283,640.

The LVI receiver circuit includes an ESD, RIN, a clamp circuit, and a receiver circuit. The ESD device is used as a protective device for signal swings below ground and for electrostatic discharge. It does not effect normal circuit operations. Resistor RIN provides unconditional stability for the LVI receiver and acts in conjunction with the clamp circuit to limit the up level voltage input to the receiver circuit.

The clamp circuit is identical to the receiver circuit except for the connection of the Schottky barrier diodes D1 and D2.

This enables an internal LVI cell to be rewired as a clamp circuit. The 'lamp circuit operates as follows: The input signal to the clamp circuit is connected to the base of transistors T1 and T3. A down level input to the clamp circuit turns off T1 and T3, thus turning off the clamp circuit. When the input signal to the clamp circuit is high, the clamp circuit simulates an LVI internal circuit by determining an LVI output voltage at the emitter of transistor T2.

When an acceptable LVI down level is reached at node 1, Schottky diode D1 turns on to pull current through resistor RIN, thus limiting the up-level voltage to the receiver circuit.

T...