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Measurement of any Circuit Delay on a Product Chip

IP.com Disclosure Number: IPCOM000049906D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Beranger, H: AUTHOR [+2]

Abstract

This article describes a method for measuring any delay on a product chip where individual circuits as master-slave latches are series connected. The measurement is made directly on the chip without using the test sites to characterize the circuits.

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Measurement of any Circuit Delay on a Product Chip

This article describes a method for measuring any delay on a product chip where individual circuits as master-slave latches are series connected. The measurement is made directly on the chip without using the test sites to characterize the circuits.

In a master/slave latch chain such as shown in the drawing, a shift-in pulse A is applied to the input S IN and a shift-out pulse C is generated at the output S OUT when clock pulse B is sufficiently wide to gate the latches. In flush mode, the total delay of the chain is obtained by measuring the time delay which elapses between the leading edges of the shift-in and shift-out pulses.

To measure the delay caused by each latch L, the pulse width of the clock signal is reduced progressively, as shown by the arrow in the drawing. From time t1, the master slave latches are locked one after the other and the shift-out pulse, instead of returning to the down level, remains at the up level as shown by the dotted lines.

When the clock is turned active again at time t2, the latches are unlocked one after the other. The first down-going transition at time t2 + xn corresponds to the unlocking of latch LN. The measurement of delay xn comprises the clock path delay plus the delay introduced by latch LN. The measurement of x(n-1) - x(n) gives the delay introduced by latch LN-1.

By reversing the shift in pulse polarity the turn-on delay can be measured.

Circuits (AND-inverts, etc.)...