Browse Prior Art Database

Suppressing Voltage Glitches in MTL Storages

IP.com Disclosure Number: IPCOM000049909D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Heimeier, HH: AUTHOR [+4]

Abstract

A circuit arrangement is described which permits controlling the switching of the read amplifier in highly integrated storages with MTL (merged transistor logic) cells. For this purpose, the bit line capacitances are simulated in the existing control logic. This prevents, above all, glitches in the output signal caused by prematurely reading an insufficient client sense signal. As with MPL semiconductor chips the read signal V-SENSE is formed relatively slowly and subject to greater delays, it is difficult to generate the optimum switching time VX of the sense amplifier by inverters.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Suppressing Voltage Glitches in MTL Storages

A circuit arrangement is described which permits controlling the switching of the read amplifier in highly integrated storages with MTL (merged transistor logic) cells. For this purpose, the bit line capacitances are simulated in the existing control logic. This prevents, above all, glitches in the output signal caused by prematurely reading an insufficient client sense signal. As with MPL semiconductor chips the read signal V-SENSE is formed relatively slowly and subject to greater delays, it is difficult to generate the optimum switching time VX of the sense amplifier by inverters. The time that passes before the read signal V-SENSE at the input of the read amplifier is sufficiently high is made up to about one-third of the delay in the peripheral control circuits and to about two-thirds of the time the storage cell requires for forming a valid sense signal V-SENSE on the relevant bit lines after selection of the word line. The time required for forming the read signal V-SENSE is essentially determined by the bit line capacitance of the storage cells.

The optimum time to switch on the read amplifier is when the read signal V- SENSE across the bit lines has reached zero. Controlling the switching time of the read amplifier only by inverters would lead to unfavorable conditions, as two thirds of the time needed for forming the read signal depend on the bit line capacitances. This time characteristic does not track with the switching speed of the inverters in the peripheral control logic. The optimum switching time of the read amplifier is controlled by an RC element (not shown) in the clock generator, whose capacitance is simulated in accordance with the bit line capacitance. For this purpose, the capacitance of the clock generator is chosen so that it simulates only the delay and tolerance generated by the bit line capacitances.

This capacitance simulated in accordance wi...