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Browse Prior Art Database

Glitchless Latch with Extendable Ports to L1 Stage

IP.com Disclosure Number: IPCOM000049916D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+3]

Abstract

The L1 stage of a latch stores a data bit according to the logic function Clock And Data equals Set and Clock And Not Data equals Reset. This logic function is a common requirement of latches in a data processing apparatus. Two transistors are each connected to pull down the base terminal of one of the two cross-connected transistors of the latch to turn off that transistor when the corresponding one of the two transistors is on. One of these transistors is connected as a diode-transistor AND-Invert gate that responds to the logic function Clock And Data. The other transistor is connected to receive the clock signal at its base terminal (like the AND-Invert stage) and to receive the data at its emitter terminal so that it turns on when the clock is up and the data is down.

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Glitchless Latch with Extendable Ports to L1 Stage

The L1 stage of a latch stores a data bit according to the logic function Clock And Data equals Set and Clock And Not Data equals Reset. This logic function is a common requirement of latches in a data processing apparatus. Two transistors are each connected to pull down the base terminal of one of the two cross-connected transistors of the latch to turn off that transistor when the corresponding one of the two transistors is on. One of these transistors is connected as a diode-transistor AND-Invert gate that responds to the logic function Clock And Data. The other transistor is connected to receive the clock signal at its base terminal (like the AND-Invert stage) and to receive the data at its emitter terminal so that it turns on when the clock is up and the data is down.

Because both of the input transistors operate by pulling down the voltage at a collector resistor, it is possible to connect any number of input circuits to the latch. The circuit avoids the common problem of glitchless circuits that the redundance that is necessary to get an overlapping operation to avoid a race condition prevents testing of certain faults in this circuit. The only untestable fault corresponds to a double defect that is highly unlikely.

A linear scan shift register is formed by a selective interconnection of a number of otherwise independent latches of a data processing element. Each latch has two stages called L1 and L2. When the latches are interconnected as a linear shift register, the L2 output of one latch is connected to the L1 input of the next latch, and a selected data pattern can be shifted serially into the processing element for testing.

In the drawing, transistors...