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Exclusive OR Circuit with Diodes Arranged to Permit Operation with Low Voltage Input Circuits

IP.com Disclosure Number: IPCOM000049917D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+2]

Abstract

In an Exclusive OR circuit of the type in which two input signals are are each applied oppositely to the base terminal of one transistor and the emitter terminal of a second transistor, the connection from each input terminal to the associated base terminal includes a diode that is poled in the direction to oppose conduction of the signal current. A resistor supplies current to the base terminal when the diode is turned off by an up-level signal at the associated input terminal. When an up-level signal is applied to one terminal and a down-level signal is applied to the other input terminal (the Exclusive OR condition), this circuit arrangement prevents the down-level signal at one input terminal from loading down the circuit that is applying an up-level signal to the other terminal.

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Exclusive OR Circuit with Diodes Arranged to Permit Operation with Low Voltage Input Circuits

In an Exclusive OR circuit of the type in which two input signals are are each applied oppositely to the base terminal of one transistor and the emitter terminal of a second transistor, the connection from each input terminal to the associated base terminal includes a diode that is poled in the direction to oppose conduction of the signal current. A resistor supplies current to the base terminal when the diode is turned off by an up-level signal at the associated input terminal. When an up-level signal is applied to one terminal and a down-level signal is applied to the other input terminal (the Exclusive OR condition), this circuit arrangement prevents the down-level signal at one input terminal from loading down the circuit that is applying an up-level signal to the other terminal. The circuit is useful with transistors that operate at a low collector-emitter voltage and in circuits in which one logic gate can be connected to apply a signal to several Exclusive OR circuits.

In the circuit of the drawing, transistors 2 and 3 and input terminals 4 and 5 are interconnected in an Exclusive OR configuration that is generally similar to the circuit in U.S. Patent 2,850,647. Transistor 6 amplifies the signal that appears at the OR connection of the collector terminals of transistors 2 and 3. Representative transistors 8 and 9 apply signals A and B to the input terminals, and...