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Exclusive NOR Circuit

IP.com Disclosure Number: IPCOM000049920D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Bansal, J: AUTHOR

Abstract

A high speed exclusive NOR circuit is shown in the figure, embodied in CMOS field-effect transistor technology. Devices P1 and P2 are enhancement mode P channel FET devices, and devices N1 and N2 are enhancement mode N channel FET devices. The source of device N1 is the logical input A, which is also connected to the gates of the devices P2 and N2. The source of the device N2 is the logical input B, which is also connected to the gates of the devices N1 and P1. The sources of the devices P1 and P2 are connected to the positive potential +VDD. The node X is shorted to the node Y and is the logical output of the circuit.

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Exclusive NOR Circuit

A high speed exclusive NOR circuit is shown in the figure, embodied in CMOS field-effect transistor technology. Devices P1 and P2 are enhancement mode P channel FET devices, and devices N1 and N2 are enhancement mode N channel FET devices. The source of device N1 is the logical input A, which is also connected to the gates of the devices P2 and N2. The source of the device N2 is the logical input B, which is also connected to the gates of the devices N1 and P1. The sources of the devices P1 and P2 are connected to the positive potential +VDD. The node X is shorted to the node Y and is the logical output of the circuit.

The following is a truth table for the circuit shown in the figure:

Input A Input B Output

0 0 1

1 0 0

0 1 0

1 1 1

The above truth table has the binary value zero denoting the down level or zero voltage and the binary one value denoting the up level or VDD voltage.

If both the inputs A and B are positive, then P1 and P2 are off and N1 and N2 are on and therefore the output will be positive. If both of the inputs A and B are down, P1 and P2 will be on and N1 and N2 will be off and therefore the output will, once again, be positive.

If the input A is down and the input B is up, then P1 is off and N1 is on, thereby applying the down level signal from the input A, through the device N1 to the output node as a down level. The voltage at node Y is approximately the same as the gate voltage on P2 and thus P2, which is an enhancement-...