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Read Only Memory Slow Zero Change Speed Tester

IP.com Disclosure Number: IPCOM000049929D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Harden, DL: AUTHOR

Abstract

This article describes a checking circuit for electrically alterable or programmable memory chips. The specific type of problem to be checked is that of a slow transition to a zero state on read out. In checking memories, after they are written with data, a slow changing bit cell that is not written with data will have no effect in the acceptability of the device. However, a slow cell for the zero transition may go undetected since a one condition (positive) exists, no speed checking is necessary, and the usual testers may overlook the fact that, indeed, the cell is intended to change to a zero upon writing. The circuit above checks for the serial transition between 400 and 500 nanoseconds after the start of a read-out cycle. This is the time period during which a slow to change zero transition will occur.

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Read Only Memory Slow Zero Change Speed Tester

This article describes a checking circuit for electrically alterable or programmable memory chips. The specific type of problem to be checked is that of a slow transition to a zero state on read out. In checking memories, after they are written with data, a slow changing bit cell that is not written with data will have no effect in the acceptability of the device. However, a slow cell for the zero transition may go undetected since a one condition (positive) exists, no speed checking is necessary, and the usual testers may overlook the fact that, indeed, the cell is intended to change to a zero upon writing. The circuit above checks for the serial transition between 400 and 500 nanoseconds after the start of a read-out cycle. This is the time period during which a slow to change zero transition will occur. The circuit selects the data bit by the use of counter 1 and decoder 2. An address is selected by the counters 11, 12, 13 and 14 connected to the input or selection gate of the electrically programmable read-only memory (EPROM) 15. Every eight steps of the data bit counter 1 cause a one-step increment in the address counters 11 through 14 to access a new 8-bit address. Data selected from the EPROM 15 on lines 16 are individually selected by AND/ORing the outputs on lines 16 individually with the data select on lines 17 by means of AND gates 3 and 4, inverters 5 and 6 and OR gate 7 so that a positive output on line 8 will be produced if any data is present for the specific bit selected.

This output on line 8 is used for gating the input to begin a sample time at latches 8A. These latches are eet by a begin sample line with a positive-going transition 400 nanoseconds into the clock cycle. This is...