Browse Prior Art Database

Metal Personalization for Read Only Storage

IP.com Disclosure Number: IPCOM000049939D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Wu, PT: AUTHOR

Abstract

Instead of having a separate diffusion contact per bit cell, the contact for two adjacent cells can be shared, thus reducing the cell area and allowing faster personalization of an FET read-only storage (ROS) chip.

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Metal Personalization for Read Only Storage

Instead of having a separate diffusion contact per bit cell, the contact for two adjacent cells can be shared, thus reducing the cell area and allowing faster personalization of an FET read-only storage (ROS) chip.

Fig. 1 shows a section of a conventional ROS array 10, having polysilicon word lines Xn, metal bit lines Bn, ground diffusion 11, and contact pads 12 having openings 13. Pads 12 form the drains of FETs 14 whose sources are grounds 11 and whose gates are word lines Xn. A bit is programmed "0" by connecting its FET's drain pad to a metal bit line by depositing a metal link in the proper opening 13; lack of such a contact programs the corresponding bit "1".

Fig. 2, drawn to the same scale as Fig. 1, shows the reduction in area possible by sharing a single contact 22 between two cells 24 of array 20. During standby, polysilicon lines Yn are precharged high (toward Vdd) while word lines Xn are held low. During addressing, one decoded Yn line is pulled low while one decoded word line Xn is driven high. A stored "0" discharges the proper output bit line Bn, while a "1" leaves it charged high.

Personalization is achieved by depositing metal links 23 in one of two positions for each cell 24. To store a "1" in any cell, its links 23 are either both connected to the adjacent Yn line or both connected to the adjacent Bn line. To store a "0", one of the links is tied to Yn and the other to Bn.

Fig. 3 is a schematic form o...