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Browse Prior Art Database

ECC System Using Linear Summing of Check Character

IP.com Disclosure Number: IPCOM000049959D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Belser, KA: AUTHOR [+5]

Abstract

The figure shows a memory system consisting of 8 independent memory cards 10, each of which includes 8 memory chips 11 such that a data word consisting of 64 failure-independent bit positions is provided when one position of the memory is addressed by the addressing circuitry 12. Each of the memory cards 10 also includes a PROM module 13 which provides a serial by bit mask stream of data which is synchronized with the data stream read from each memory chip. The serial by bit mask streams from the cards together define a mask byte associated with the addressed location in memory so as to define which bit positions of the 64-bit data word are defective for that address. This information is determined and recorded in PR0M independently for each card at the time of manufacturing.

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ECC System Using Linear Summing of Check Character

The figure shows a memory system consisting of 8 independent memory cards 10, each of which includes 8 memory chips 11 such that a data word consisting of 64 failure-independent bit positions is provided when one position of the memory is addressed by the addressing circuitry 12. Each of the memory cards 10 also includes a PROM module 13 which provides a serial by bit mask stream of data which is synchronized with the data stream read from each memory chip. The serial by bit mask streams from the cards together define a mask byte associated with the addressed location in memory so as to define which bit positions of the 64-bit data word are defective for that address. This information is determined and recorded in PR0M independently for each card at the time of manufacturing. The cards 10 are interchangeable, and any card can be replaced at any time as repair warrants it.

As shown, the mask byte is supplied to the decoder 15 which, in turn, controls the memory read/write system 16A-16B to prevent data from being stored at that address in memory and/or substitute good bit storage locations in an auxiliary memory for any defective storage locations in the main memory that have been defined by the mask byte to be defective. Any known prior-art system for mapping defective bit locations to good locations in the auxiliary memory may be employed.

It is desirable to insure that the serial by bit mask train from each chip is absolutely correct and does not contain any errors.

Each data stream from the chip representing mask bits is, therefore, protected by a separate and distinct check character which is stored in the PR0M 13 and which will determine the occurrence and location and type of error that may occur in the...