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Digital High Frequency Doubler Circuit

IP.com Disclosure Number: IPCOM000049974D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Roach, SW: AUTHOR

Abstract

Frequency doubling is not new. For most simple applications, a retriggerable single-shot is used which fires on both the rising and falling edges of the input signal. A more complicated implementation involves using a voltage-controlled oscillator, a divide by N counter, a phase comparator, and a low-pass filter, all in a phase-locked loop configuration.

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Digital High Frequency Doubler Circuit

Frequency doubling is not new. For most simple applications, a retriggerable single-shot is used which fires on both the rising and falling edges of the input signal. A more complicated implementation involves using a voltage- controlled oscillator, a divide by N counter, a phase comparator, and a low-pass filter, all in a phase-locked loop configuration.

For frequency doubling in high speed digital applications, standard TTL (transistor transistor logic) single-shots do not have sufficiently narrow pulse widths. Phase-locked loop-type doublers are often too complex and cumbersome for use in simple circuits.

The frequency doubler described overcomes these limitations. A complementary output element 12 provides two signals A and B 180 degrees out of phase. This eliminates the skew which would result from the propagation delay of an inverter used for the same purpose.

The rising edges of signals A and B are used to trigger data latches 15 and 16, respectively. Each latch is normally in the reset state. With the data input tied high, the trigger causes the latch to toggle to the set state.

The duty cycle of the output signal is determined by the amount of delay used in the feedback signals from the Q output to the CLEAR input. A 20 ns delay can be used to give an approximate 50 percent duty cycle. When the low signals at the Q output propagate through the delay to the CLEAR input, the flip-flop is returned to its reset state. T...