Browse Prior Art Database

MOSFET Structure

IP.com Disclosure Number: IPCOM000049992D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR [+3]

Abstract

This article describes a MOSFET structure with minimal parasitics for high performance application. It is also suitable for implementing latch-up free CMOS (complementary MOS) circuits. Fig. 1 shows a cross-sectional view of the new MOSFET structure. A major feature of this structure is that it has buried polysilicon regions 2,3 insulated, for example, by silicon dioxide regions which are disposed over and under regions 2,3.

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MOSFET Structure

This article describes a MOSFET structure with minimal parasitics for high performance application. It is also suitable for implementing latch-up free CMOS (complementary MOS) circuits. Fig. 1 shows a cross-sectional view of the new MOSFET structure. A major feature of this structure is that it has buried polysilicon regions 2,3 insulated, for example, by silicon dioxide regions which are disposed over and under regions 2,3.

The opening 6 of buried oxide layer 5 is self-aligned to the edges of the buried polysilicon regions 2,3 which act as contacts to source and drain junctions 7,8, respectively. Buried oxide layer 5 minimizes the source and drain capacitance. In addition, since only a sidewall junction of the source 7 and drain 8 remains in this new structure, the carrier injection from drain 8 (and source 7) downward into the substrate 9 is mostly eliminated. Thus, the MOSFET structure of Fig. 1 is extremely well suited for CMOS applications.

Figs. 2 and 2A show a cross-sectional view and schematic, respectively, of one kind of CMOS circuit implemented with the structure of Fig. 1. The two types of polysilicon (p+ and n+) at the OUT terminal of the CMOS gate can be physically connected together so the distance between the P-MOS and N-MOS can be reduced and only one contact hole to the OUT terminal is needed. Thus, the gate pitch can be reduced significantly.

One method for fabricating the MOSFET of Fig. 1 is outlined in Figs. 3A-3G. It is similar to the process used to fabricate a symmetrical bipolar structure (D.D. Tang et al., "A Symmetrical Bipolar Transistor Structure," IEDM, 58-60 (1980).

The process uses only 4 masks. It is at least one mask fewer than the usual MOS buried contact process.

In Fig. 3A, layers of silicon dioxide and n+ polysilicon are formed using well known oxidation and deposition (chemical vapor deposition of silicon) processes.

In Fig. 3B, employing a first masking step, portions of the upper oxide...