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Simple Parallel Adapter for a Logic Simulation Machine

IP.com Disclosure Number: IPCOM000050029D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Miranker, GS: AUTHOR

Abstract

A parallel adapter for interfacing randomly arriving serial input signals into a parallel format for provision to a logic simulation device is set forth. The input signals are provided for a shift register which operates under the control of a control device and instruction memory for keeping track of when the input signals are provided, and for providing same in parallel to a multiplexer for provision in parallel to a logic simulation device.

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Simple Parallel Adapter for a Logic Simulation Machine

A parallel adapter for interfacing randomly arriving serial input signals into a parallel format for provision to a logic simulation device is set forth. The input signals are provided for a shift register which operates under the control of a control device and instruction memory for keeping track of when the input signals are provided, and for providing same in parallel to a multiplexer for provision in parallel to a logic simulation device.

There are two general uses for a logic simulation machine (LSM), simulation of simple control hardware for slow peripheral devices, such as printers.

A LSM to accomplish this could consist of a small number of logic processors. If one or two suffice, a switch is not necessary.

A LSM may need a parallel adapter for array simulation and for driving peripheral devices. A simple parallel adapter data attachment (SPAD) is shown in the figure. Operation of the SPAD on the outbound side is as follows: 1. The instruction memory (IM)2. on each instruction cycle

determines whether or not the signal available from the

switch (not shown) is to be loaded into serial in/ parallel

out shift registers 4 and 6. That command together with the

phase bit (indicating whether the current simulation cycle

is an "A" or "B" phase cycle) and the mode flag (which

indicates unit delay versus rank order simulation) select

which of the two shift registers is to be loaded.

2. The SPAD includes a smal...