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Cache Organization with Various Line Sizes

IP.com Disclosure Number: IPCOM000050033D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Tan, KG: AUTHOR

Abstract

From simulation data, it is well known that for a given size and organization of CPU cache, the buffer miss ratio (BMR) decreases as the line size increases. It is also known in a given cache organization that instruction references have lower BMRs than data references. Since instructions are of a "read-only " nature, it is advantageous to keep the line size long. The data references are subject to change, and are shared among processors in a MP (multiprocessor) environment. Therefore, it is better to make the data line size small for MP considerations. This article describes a central cache organization which provides long lines for instructions and short lines for data references (Fig. 1).

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Cache Organization with Various Line Sizes

From simulation data, it is well known that for a given size and organization of CPU cache, the buffer miss ratio (BMR) decreases as the line size increases. It is also known in a given cache organization that instruction references have lower BMRs than data references. Since instructions are of a "read-only " nature, it is advantageous to keep the line size long. The data references are subject to change, and are shared among processors in a MP (multiprocessor) environment. Therefore, it is better to make the data line size small for MP considerations. This article describes a central cache organization which provides long lines for instructions and short lines for data references (Fig. 1).

Data references proceed like conventional cache. Data is read from cache if found in cache, or a data line (D) is fetched from main memory if not found in cache. It is in the instruction references that this organization deviates from conventional cache organizations. Let data line size equals D bytes (D ranges from

64-256 bytes), and instruction line size equals

n ' D bytes (n=2, 4, . . . 2/a/). Each D byte

of the instruction line is called a segment.

During I-fetches, an instruction line request is initiated to memory. Except for the first segment, all segment addresses and their associated data are loaded in the address array and data line array (Fig. 2). Data in the data line array will load into cache only when it is needed and referenced. For example, let n=2. When I-fetch miss occurs, a memory request for a line of 2D bytes is initiated. The first segment of the line (0-D bytes) is returned to the data cache, and the cache directory properly updated. The second segment of t...